1. Field of the Invention
The present invention relates to a junction type field effect transistor and a method of manufacturing the same. More specifically, the present invention relates to an improvement in a junction type field effect transistor employing a compound semiconductor and providing a junction between the semiconductor and an intermediate metallic compound in a metal oxide film, at a region having lateral dimensions substantially identical to a metal gate electrode used in the transistor.
2. Description of the Prior Art
One example of a junction type field effect transistor which constitutes the background of the invention comprises a normally off type gallium arsenide field effect transistor. A gallium arsenide field effect transistor operates at a higher speed than a silicon field effect transistor, inasmuch as a gallium arsenide field effect transistor utilizes gallium arsenide as a basic material, which has an electron saturation velocity more than two times larger than that of silicon and has an electron mobility four to five times higher than that of a silicon field effect transistor. Accordingly, it is expected that implementation of an integrated circuit with gallium arsenide field effect transistors achieves an operation thereof higher in speed than that of a silicon integrated circuit currently available. Gallium arsenide integrated circuits include two types, one employing normally-on type (depletion type) gallium arsenide field effect transistors as basic active devices and the other employing normally-off type (enhancement type) gallium arsenide field effect transistors as basic active devices. An integrated circuit employing normally-off type field effect transistors is characterized by a simple circuit configuration and law power consumption. As shown in FIG. 1, a field effect transistor in such a case typically employs a so-called MES type structure or a MES field effect transistor wherein a drain to source current is controlled by a Schottky gate electrode 5 formed on the surface of an n-type gallium arsenide active layer 2 at the area between a source electrode 3 and a drain electrode 4 both formed on the gallium arsenide n-type active layer 2. A normally-off type field effect transistor has a depletion layer 6 immediately beneath the gate electrode 5 with the outermost region thereof extending to reach the interface between a substrate 1 of a seminsulating material such as gallium arsenide and the n-type active layer 2 when the gate bias is zero, whereby complete interruption is established between the source electrode 3 and the drain electrode 4 and no drain current flows therebetween. When the gate electrode 5 is biased in the positive direction, the depletion layer 6 becomes thinner so that a drain current starts to flow. As the gate voltage is increased, the drain current is accordingly increased; however, since the positive voltage being applied to the gate electrode 5 is limited, the drain current becomes saturated at a predetermined value. The drain current is proportional to (a-d), where "a" denotes the width of the depletion layer 6 immediately beneath the gate when the bias is zero and "d" denotes the width of the depletion layer when the gate voltage is applied. The width d is given as K (V.sub.bi -V).sup.1/2 in the case of a Schottky barrier gate, where K is a constant proportional to the carrier density and the dielectric constant of the active layer 2, V.sub.bi represents a built-in voltage and V represents the applied voltage (positive). Accordingly, the drain current increases as the positive voltage V applied to the gate electrode 5 is increased and hence the width d of the depletion layer is decreased, while the same is saturated at V=V.sub.bi.
Meanwhile, the switching speed of a gallium arsenide field effect transistor is increased as the drain current is increased. The drain current is increased by increasing V.sub.bi. In the case of a Schottky barrier gate, V.sub.bi is approximately 0.6V and it is difficult to increase the same any more. However, V.sub.bi can be increased by implementing the gate electrode 5 as a p-n junction type and accordingly the drain current can also be increased.
FIG. 2 is a sectional view showing a conventional junction gate gallium arsenide field effect transistor having a p-type layer 7 formed immediately beneath the gate electrode 5 through a diffusion method. In the case of a p-n junction gate, the width d is given as K (V.sub.bi -V).sup.1/3. In this case, V.sub.bi is 0.9 to 1.0V and is higher by 0.3 to 0.4V than that in case of a Schottky barrier type gate. The p-type layer 7 can be formed in the n-type layer 2 formed at the area between both the source and drain electrodes 3 and 4 through a diffusion method or an ion implantation method. Since any diffusion method or ion implantation method requires a high temperature process, the gate length is prolonged beyond a desired length, resulting in a possibility of a degraded high frequency characteristic of the resultant field effect transistor. Propriety or impropriety of a high frequency characteristic of a field effect transistor is determined as a function of a current gain cutoff frequency f.sub.t, which is proportional to g.sub.m D.sub.gs, where gG.sub.m is a transconductance and C.sub.gs is a capacitance between the gate and source electrodes. A p-n junction gate field effect transistor formed as described above has a width d of a depletion layer proportional to the 1/3 power of the applied voltage and therefore has g.sub.m smaller than, and C.sub.gs larger than those of a Schottky barrier gate field effect transistor. Therefore, while a p-n junction gate field effect transistor has an increased switching speed in a relatively low frequency, the same has a degraded switching speed in a high frequency region.